參數(shù)資料
型號(hào): M62320GP
元件分類: 微控制器/微處理器
英文描述: 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝: 4.40 X 5 MM, 0.65 MM PITCH, PLASTIC, SSOP-16
文件頁(yè)數(shù): 10/11頁(yè)
文件大?。?/td> 136K
代理商: M62320GP
M62320GP
REJ03D0909-0100 Rev.1.00 Mar 25, 2008
Page 8 of 10
In case the I/O setting is different between each terminals.
An example: the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals,
respectively.
SDA
SCL
A1 A0
A2
1
11
00
A
P2 P1
P3
P5 P4
P6
P7
P0
A D17 D16 D15 D14 D13 D12 D11 D10
D27 D26 D25 D24 D23 D22 D21 D20
A
D2X
D1X
Hi-Z
D0
to
D3
DATA
Hi-Z
D4
to
D7
SDA
SCL
1234567
8
1234567
12345678
A1 A0
A2
1
11
1
0A
A
Hi-Z
D4 to D7
output
DATA
D1X
D2X
D3X
D4X
D4 to D7
(instance)
D0 to D3
Start
condition
Start
condition
Slave address
I/O setting
Data output
Stop
condition
Stop
condition
Data latch
D17 D16 D15 D14 D13 D12 D11 D10
D37 D36 D35 D34 D33 D32 D31 D30
D47 D46 D45 D44 D43 D42 D41 D40
Write mode
The terminal assigned as an output provides the data written in the output data latch.
After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are output after
the I/O setting has been done. Finally the assigned output are provided after the 8-bit data transmission.
The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data setting.
Read mode
The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the terminal
assigned as an input, and then the latched data is output via the SDA line.
The data of the output assigned terminal is also handled in the same procedures as above.
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