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參數(shù)資料
| 型號： | M62320P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDIP16 |
| 封裝： | 6.30 X 19 MM, 2.54 MM PITCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 149K |
| 代理商： | M62320P |
M62320P/FP
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 4 of 10
I
2C BUS Characteristics
Limits
Item
Symbol
Min
Max
Unit
SCL clock frequency
fSCL
0
100
kHz
Free time: the bus must be free before a new transmission can start
tBUF
4.7
—
s
Hold time START Condition
After this period, the first clock pulse is generated.
tHD:STA
4.0
—
s
Low period of the clock
tLOW
4.7
—
s
High period of the clock
tHIGH
4.0
—
s
Set-up time for START condition
Only relevant for a repeated START condition
tSU:STA
4.7
—
s
Data Hold time
tHD:DAT
0
—
s
Data Set-up time
tSU:DAT
250
—
ns
Rise time of SDA and SCL signals
tR
—
1000
ns
Fall time of SDA and SCL signals
tF
—
300
ns
Set-up time for STOP condition
tSU:STO
4.0
—
s
Note:
Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Timing Chart
VIH
tBUF
tSU:STO
tSU:STA
tHD:DAT
tSU:DAT
tHD:STA
Start
Stop
tHIGH
tLOW
tR, tF
VIL
SDA
VIH
VIL
SCL
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