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參數(shù)資料
| 型號(hào)： | M63016HBFPC050.000000MHZ |
| 廠商： | MTRONPTI |
| 元件分類： | XO, clock |
| 英文描述： | TCXO, CLOCK, 50 MHz, PECL OUTPUT |
| 封裝： | ROHS COMPLIANT, LEADLESS, CERAMIC PACKAGE-6 |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 401K |
| 代理商： | M63016HBFPC050.000000MHZ |
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Please see www.mtronpti.com for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI 1-800-762-8800.
M630x Series
5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/CMOS, TCXO/TCVCXO
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions/Notes
Frequency Range
F
50
1400
MHz
LVPECL, LVDS, CML (Note 4)
50
135
MHz
CMOS
Operating Temperature
TA
See Ordering Information
°C
Storage Temperature
TSTG
-55
+125
°C
Frequency Stability
See Ordering Information
ppm
See Note 1
Frequency Tolerance at +25°C
-1.0
+1.0
ppm
Frequency Vs. Aging
-3.0
-1.0
+ 3.0
+ 1.0
ppm
1
st year
Per year thereafter.
Frequency Vs. Supply Voltage
± 0.4
ppm
5% voltage variation
Frequency Vs. Reflow
±
0.75
ppm
2 reflows max.
Frequency Vs. Load
± 0.2
ppm
5% supply voltage variation
Operating Voltage
Vcc/Vs/Vdd
3.135
3.3
3.465
V
M6300
2.375
2.5
2.625
V
M6301
1.71
1.8
1.89
V
M6302
Operating Current
ICC
125
mA
LVPECL
100
mA
LVDS
110
mA
CML
90
mA
CMOS
Rise/Fall Time
Tr/Tf
0.35
ns
PECL, LVPECL, LVDS
6
ns
CMOS
Logic “1” Level
VOH
VCC-1.02
90% Vdd
V
LVPECL
CMOS
Logic “0” Level
VOL
VCC-1.63
10% Vdd
V
LVPECL
CMOS
Common Mode Output Voltage
Vcm
1.2
V
LVDS
Symmetry (Duty Cycle)
45
55
%
@ 50% Vdd (CMOS)
@ 50% of waveform (LVPECL)
@ 1.25 V (LVDS)
Output Voltage Level
0.7
0.95
1.2
Vp-p
CML
Tuning Range
± 5
ppm
VCTCXO only. See Note 2.
Output Skew
20
15
20
ps
LVPECL
CML
LVDS
Output Load
50
to (V
CC-2)
VDC 100
Differential
See Note 3
LVPECL
LVDS, CML
15
pF
CMOS
Enable/Disable Function
80%
0.5
V
Outputs enabled (Option B or G)
Outputs disabled
Outputs enabled (Option S or M)
Outputs disabled
Phase Noise (Typical)
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Offset from carrier
E
le
c
tr
ic
a
lS
p
e
c
if
ic
a
tio
n
s
@ 622.080 MHz (LVPECL)
@ 100.000 MHz (HCMOS)
@ 50.000 MHZ (HCMOS)
-60
-73
-80
-90
-97
-102
-120
-123
-130
-127
-131
-137
-133
-136
-141
dBc/Hz
Shock
Per MIL-STD-202, Method 213, Condition C
Vibration
Per MIL-STD-202, Methods 201 & 204
Solderability
Per EIAJ-STD-002
Hermeticity
1 X 10
-8 atm cc/sec of helium (Crystal only)
Thermal Shock
Per MIL-STD-883, Method 1011, Condition A
E
n
v
ir
o
n
m
e
n
ta
l
Thermal Cycle
Per MIL-STD-883, Method 1010, Condition B
Note 1: Contact factory for less than ± 1ppm frequency stability.
Note 2: Contact factory for other Tuning Range options.
Note 3: See Load Circuit Diagram in this data sheet.
Note 4: Contact factory for frequencies over 945 MHz.
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