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參數(shù)資料
| 型號： | M64893GP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR |
| 中文描述： | 串行輸入鎖相環(huán)頻率合成器的電視/錄像機(jī) |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 49K |
| 代理商： | M64893GP |
MITSUBISHI IC
S
(TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
5
METHOD OF SETTING DATA
The frequency demultiplying ratio uses 15bits. Setting up the band
switching output uses 4bits.
The test mode data uses 8bits. The total bits used is 27bits. Data is
read in when the enable signal is "H" and the clock signal falls.
The band switching data is read in at the 4th pulse of the clock
signal. The program counter data is read into the latch by the fall of
the 19th pulse of the clock signal. When the enable signal goes to
"L" before the 19th pulse of the enable signal, only the band SW
data is updated and other data is ignored.
The data is latched at the 19th pulse of the clock signal. At this time,
1/640 frequency division ratio is used. Clock signals after the above
are invalid.
M8
BS4
BS3
BS2
BS1
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
4
2
3
2
2
2
1
2
0
ENA
DATA
CLK
BAND SW
DATA
READ INTO LATCH
M COUNTER DIVISION
RATIO SETTING
S COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
M7
M6
M5
M4
M3
M2
M1
M0
S4
S3
S2
S1
S0
M9
2
9
HOW TO SET THE DIVIDING RATIO OF THE
PROGRAMMABLE DIVIDER
Total division N is given by the following formulas in addition to the
prescaler used in the previous stage.
N=8 (32M+S) M: 10 bit main counter division
S: 5 bit swallow counter division
The M and S counters are binary the possible ranges of division
are as follows.
32
≤
M
≤
1023
0
≤
S
≤
31
Therefore, the range of division N is 8,192 to 262,136.
The tuning frequency f
VCO
is given in the following equations.
f
VCO
=f
REF
×
N
=6.25
×
8
×
(32M+S)
=50.0
×
(32M+S) [kHz]
But, the tuning frequency range is 51.2MHz to 1300MHz from the
maximum prescaler operating frequency.
TEST MODE DATA SET UP METHOD
The data for the test mode uses 20 to 27bits. Data is latched when
the 27th clock signal falls.
(1) When transferring 3-wire 27 bit data
ENA
T2
T1
T0 RSa RSb OS
TEST DATA SETTING
CLK
SI
CP
BAND SW
DATA
M COUNTER DIVISION
RATIO SETTING
S COUNTER
DIVISION
RATIO SETTING
1
19
20
27
READ INTO LATCH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M64894 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR |
| M64894FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR |
| M64894GP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Serial Input PLL Frequency Synthesizer for TV/VCR |
| M64895BFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:PC BUS FREQUENCY SYNTHESIZER FOR TV/VCR |
| M64895BGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:I2C BUS FREQUENCY SYNTHESIZER FOR TV/VTR |
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