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參數(shù)資料
| 型號： | M65677FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | DIGITAL NTSC/PAL ENCODER |
| 中文描述： | 數(shù)字的NTSC / PAL編碼器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 38K |
| 代理商： | M65677FP |
MITSUBISHI ICs (TV)
M65677FP
DIGITAL NTSC/PAL ENCODER
5
DESCRIPTION OF PIN
Pin No.
Pin name
(cont.)
Type
Function
42
Ccomp
I
Phase compensation for chroma or V output DAC.
It should be connected to the analog ground via a capacitor.
Chroma or V signal output.
The DAC output should be connected to the analog supply via a load resistor (R
The output amplitude is set up by reference resistor (Rref) and RL.
Supply Analog supply for DACs.
Supply Analog ground for DACs.
Luma or U signal output.
It should be connected to the analog supply via a load resistor (RL).
The output amplitude is set up by reference resistor (Rref) and RL.
A reference current source for chroma or V signal output DAC.
It should be connected to the analog supply via a reference resistor (Rref).
A reference current source for Y or U DAC.
It should be connected to the analog supply via a reference resistor (Rref).
Phase compensation for Y or U DAC.
It should be connected to the analog ground via a capacitor.
No connection.
Supply Digital supply for the internal logic.
Supply Digital ground for the internal logic.
System clock output.
It must be in no connection except for a connection to a X'tal oscillator.
System clock input.
The clock frequency is only 27.0MHz.
Supply Digital ground for the I/O.
43
DAC
O
L
).
44
45
AV
AV
DD1
SS1
46
DAY
O
47
Cref
I
48
Yref
I
49
Ycomp
I
50
51
52
N.C.
DV
DD1
DV
SS1
53
Xout
O
54
Xin
I
55
56
57
58
59
60
61
62
63
64
DV
SS2
PXD7
PXD6
PXD5
PXD4
PXD3
PXD2
PXD1
PXD0
DV
DD2
I
Pixel data inputs.
The acceptable video data are;
multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV, defined in
CCIR Rec656
multiplexed video data (Y/Cb/Cr) defined in CCIR Rec601
MSB and LSB is PXD7 and PXD0, respectively.
Supply Digital supply for the I/O.
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