參數(shù)資料
型號： M65727FP
廠商： Mitsubishi Electric Corporation
英文描述： MPEG2 MOTION ESTIMATION LSI
中文描述： 大規(guī)模集成電路的MPEG2運(yùn)動估計
文件頁數(shù)： 21/55頁
文件大?。?/td> 242K
代理商： M65727FP
DISTRIBUTION RESTRICTED. COPYRIGHT RESERVED 1995
CONTACT MITSUBISHI ELECTRONICS REGARDING DISTRIBUTION
21
Fig. 4.3.1-1 shows the input operation of the search window image.
4.3.2 Search Window Image Input for Dual-Prime mode
The search window image for Dual-Prime can be input in parallel and independent of motion
estimation operation. The search window image input for Dual-Prime starts at the cycle proceeding the
cycle in which the sync signal SSYNC is asserted. The M65727 uses 108 valid cycles for the first
search window when the Field Dual-Prime mode is ON. After the first search window is complete the
SSYNC is asserted to begin the input of the second search window.
When the Frame Dual-Prime estimation Mode is used, there will be 72 valid cycles for the first search
window, also 72 valid cycles for second search window. The valid cycle means the cycle whose input
data is specified as valid by DENSWC.
The search window image input data used for Dual-Prime is input in the order according to the raster
scan starting from the upper left of the screen. Four vertical adjacent pixels are input simultaneously
using 32 bit DSWI.
The data input must be completed within one execution cycle and at least 10 cycles or more space is
needed between ESYNC and SSYNC. As long as this limitation is obeyed, the search window image
input for Dual-Prime can be run in parallel with the input of the template MB data and the actual
operation of the motion estimation.
Fig. 4.3.2-1 shows the search window image data input operation used for Dual-Prime.
4.3.3 Template MB Data Input
Inputting the template MB data can be performed independent of and in parallel with the motion
estimation operation. Excluding Frame Dual-Prime mode, the template MB data of M65727 requires
256 pixels per 1 macro block. In case of Frame Dual-Prime Estimation Mode, template MB includes
128 pixels, but, 256 pixels (of which the last 128 pixels are dummy pixels) are needed. Inputting
the template MB data starts at the cycle proceeding the cycle in which the sync signal MSYNC is
asserted and continues for 256 valid cycles. The valid cycle refers to the cycle whose input data is
specified as valid by the data enable specifying signal, DENMBC. It is possible, using this data enable
specification, to do no wait data transfer using SRAM as frame memory. For lower cost
implementation when DRAM is used as frame memory, wait states are useful to allow slower data
transfer.
The template MB data is input by scanning from the upper left-hand corner in vertical direction.
The data input must be completed within one execution cycle and at least 10 cycles or more space is
needed between ESYNC and MSYNC. As long as this limitation is obeyed, the template MB input
can be run in parallel with the actual arithmetic operation of motion estimation and the search window
image input.
Fig. 4.3.3-1 shows the input operation of the template MB data.
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