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參數(shù)資料
| 型號(hào)： | M66006P |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 12-BIT I/O EXPANDER |
| 中文描述： | 12位I / O擴(kuò)展 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 102K |
| 代理商： | M66006P |
2
MITSUBISHI
DIGITAL ASSP
M66006P/FP
12-BIT I/O EXPANDER
FUNCTION
The M66006 realizes low power dissipation and high noise
immunity by applying silicon CMOS process.
Because a 12-bit serial-parallel shift register and a 12-bit par-
allel-serial shift register are independently built in this IC, it is
possible to read serial input data while converting parallel
data into serial data.
When CS changes from “H” to “L”, serial output of 12-bit par-
allel data and read of serial data from the MCU start. That is,
12-bit parallel data is latched at the falling edge of CS, syn-
chronized with the falling edge of shift clock, and then output
to serial output pin DO as serial data. At the same time, serial
data from the MCU is read to the internal shift register at the
rising edge of shift clock. The shift clock on and after 13th bit
is neglected and pin DO is put in the high impedance state
when the reading operation is masked. When CS changes
from “L” to “H”, 12-bit serial data read into pin DI is output to
parallel output pins from D1 to D12.
Because the output form of parallel output pins is N-channel
open drain output, “H” must be written to the pin to set to in-
put mode.
DESCRIPTION OF OPERATION
(1)When power is supplied, pins DO and from D1 to D12 are
in undefined state. When S changes to “L”, those pins are
in high impedance state.
(2)At the falling edge of CS, the status of pins from D1 to D12
is loaded to shift register
!
.
(3)At the falling edge of CLK, data which is loaded as above
(2) is output to pin DO as 12-bit serial data in order.
(4)At the rising edge of CLK, 12-bit serial data is written from
DI to shift register
@
.
(5)CLK on and after the 13th bit is neglected and writing of
serial data is not possible. Also, DO is put in the high im-
pedance state.
(6)At the rising edge of CS, the data which is written as men-
tioned in (4) is output to pins from D1 to D12.
(7)Shift register
!
loads the data applied externally and the
AND-tie data latched by the parallel output latch.
(8)When CS rises before CLK reaches the 12th bit, the paral-
lel output latch latches the data which has been written to
shift register
@
and outputs it to pins from D1 to D12. In
this case, shift registers
!
and
@
continues the shift op-
eration and DO outputs serial data until CLK reaches the
12th bit.
(9)Switching of I/O mode of pins from D1 to D12 is controlled
by the serial data which is input to pin DI. Pins to which “H”
is written operates as input pins.
OPERATION TIMING DIAGRAM
1
CLK
CS
S
L
H
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
DO10
DO11
DO12
DI1
DI
DO
DI1
DI2
DI12
D1
D2
DI2
DO1
DO2
DO12
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12
2
3
4
5
6
7
8
9
10
11
12
13
(2)
(4)
(6)
(3)
(5)
(6)
(1)
High impedance
1 cycle
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