參數(shù)資料
型號: M66239FP
元件分類: 時鐘產(chǎn)生/分配
英文描述: OTHER CLOCK GENERATOR, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 25/26頁
文件大?。?/td> 322K
代理商: M66239FP
M66239FP
Rev.1.00 Mar 16, 2005 page 6 of 23
Function Summary
Sync Clock Generation Function
M66239FP has standard clock generator function, it is able to output clock in sync with external trigger TR. And it
features excellent synchronizing precision (sync accuracy: jitter) over a wide range frequency band.
Sync clock output timing is determined by trigger input signal edge. Trigger edge polarity (positive/negative) is
selectable by MODE input.
Time-lag between trigger input signal edge and sync clock output equals the sum of clock input signal "L" pulse width
and M66239FP internal delay.
Variation in this lag (
t) is ±1.5ns, ensuring excellent synchronizing accuracy.
There are three types of outputs: synchronous clock output (CKO), synchronous clock inverted output (CKOB), and
one-shot pulse output (PULSE).
Synchronous clock output CKO is the same frequency as clock input signal MCLK. Synchronous clock inverted output
CKOB is inverted signal of sync clock CKO. PULSE is one-shot pulse output which is almost equal to two cycles. All
three sync outputs are suspended when trigger input signal is on "H" level when MODE is "H", and "L" level when
MODE is "L" level. During these period, CKO and PULSE stay on "L" level, CKOB stay on "H" level.
Also, start phase of 3 sync. clocks are controlled by T/8 steps (T: Clock Period).
T/8 steps resolution is controlled by serial resister setting.
M66239FP integrate four synchronizing clock generator macro with frequency synthesizer function.
Frequency Modulation Function
M66239FP is able to modulate sync. clock frequency.
Frequency modulation profile is controlled by serial resister. Serial resister is controlled by serial input clock (SCLK),
serial input enable (SENABLE) and serial input data (SDATAIN).
When SENABLE is "L" level, SDATAIN is able to write to serial input resister by SCLK. SDATAIN is composed by
4 bit address + 3 bit W/R distinction + 16 bit resister data.
After write operation completed, it can be able to confirm the resister status using read operation to serial input resister.
Resister setting is as follows.
(1) Operation mode
: Resister 1
(2) Frequency modulation period (Trate)
: Resister 2
(3) Frequency modulation start position (Tstart)
: Resister 3
(4) Output center frequency (fcenter)
: Resister 4
(5) Output peak frequency (fpeak)
: Resister 5
(6) 1st.pole position (1stPole)
: Resister 6
(7) 2nd.pole position (2ndPole)
: Resister 7
(8) 3rd.pole position (3rdPole)
: Resister 8
(9) 4th.pole position (4thPole)
: Resister 9
(10) 1st.Pole frequency (f1stPole)
: Resister 10
(11) 3rd.Pole frequency (f3rdPole)
: Resister 11
There are four operation modes, center frequency offset type modulation (mode1), triangle type modulation (mode2 and
3), and polygon type modulation (mode4).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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