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參數(shù)資料
| 型號： | M66242FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4-CH 12-BIT PWM GENERATOR |
| 中文描述： | 4通道12位PWM發(fā)生器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 109K |
| 代理商： | M66242FP |
4
MITSUBISHI
DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
OPERATION
Serial Data Input
When chip select CS is “L” and write control input WR is “L”,
data input to S
IN
at the edge where write clock input S
CLK
sta-
tus shifts from “L” to “H” is written. (See Fig. 3.)
At the edge where WR rises from “L” to “H”, the latest 8-bit
data writing is completed, and input data is stored in lower (or
upper) byte register. When writing on the lower byte or writing
on both upper and lower bytes is completed, data on the
lower byte register or, in the latter case, data on both lower
and upper byte registers is written on the PWM register of the
channel designated by lower bytes b2 and b1. All setting pro-
cess ends with this writing, and PWM waveform changes ac-
cording to the setting from the next cycle.
PWM Waveform Output
(1)12-bit PWM output
One PWM waveform cycle is divided into 16(2
4
) subsec-
tions t, and each subsection is further divided into 256 (2
8
)
minimum resolution bits
τ
(= 2/f
XIN
)
The “H” width of subsection t basic waveform is deter-
mined by the upper 8 bits of PWM data.
(In Fig. 2 above, “H” width is 4A
16
= 74
×
τ
)
Among these 16 subsections t, subsections t
m
designated
by the lower 4 bits of PWM data have “H” width that is
longer by
τ
.
[In Fig. 2 above, the “H” width of designated 6 subsections
(m =2, 4, 6, 10, 12 and 14) is 4B
16
= 75
×
τ
.]
Fig. 2 PWM Waveform Output Example (Input data: 4A6 16)
0
1
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
1
0
b7
b0
b7
b0
b11
b4
b3
b0
Upper byte register
Lower byte register
PWM register
4A6
16
Determines “H” width of basic waveform
(In this case, “H” width is 4A
16
= 74)
Determines subsections t
m
whose
“H” width is increased by
the minimum bit width of
τ
(Refer to Table 2.)
(In this case, m = 2, 4, 6, 10, 12 and 14.)
Basic waveform
(e.g. When f
XIN
is 4 MHz,
= 0.5
μ
s)
τ
×
74
τ
τ
=
2
f
XIN
One subsection
t =
τ
×
256
(8-bit resolution)
Designated subsection
t
m
(In this case, m = 2, 4, 6, 10, 12 and 14.)
τ
Output waveform
Subsection
One cycle
t
0
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
15
τ
×
74
τ
×
75
τ
×
74
τ
×
74
τ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66242P | 4-CH 12-BIT PWM GENERATOR |
| M66244FP | High Speed Monolithic Pulse Width Modulator |
| M66250 | 5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250FP | 5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250P | 5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66242P | 制造商:Renesas Electronics Corporation 功能描述: |
| M66244FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:High Speed Monolithic Pulse Width Modulator |
| M66250 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120*8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120*8-BIT LINE MEMORY(FIFO/LIFO) |
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