M66307SP/FP
LINLINE SCAN BUFFER with 16BIT MPU BUS COMPATIBLE INPUTS
1
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
CLK/
φ
IN
(0V)GND
WR
CS
C/D
RESET
INTR
CLKE
WRITE CONTROL
INPUT
CHIP SELECT INPUT
COMMAND/DATA
CONTROL INPUT
RESET INPUT
INTERRUPT REQUEST
OUTPUT
CLOCK INPUT
CLOCK ENABLE
INPUT
DATA INPUTS
D
7
V
CC
(5V)
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DACK
DREQ
EXD
TOG
CLK/
φ
OUT
DATA OUT
BUSY/ORDY
DMA ACKNOWLEDGE
INPUT
DMA REQUEST
OUTPUT
EXTENDED D INPUT
TOGGLE INPUT
CLOCK
OUTPUT
DATA OUTPUT
BUSY/
OUTPUT
READY
OUTPUT
DATA INPUTS
MITSUBISHI
DIGITAL ASSP
DESCRIPTION
The M66307SP/FP is an integrated circuit consisting of a line buffer
with static memory, manufactured by the silicon gate CMOS pro-
cess, which satisfies A3-paper 400DPI requirements. It converts the
stored data from the 16-bit MPU bus into serial data and outputs it at
a transfer rate of up to 10Mbps synchronously with the external data
request clock or an arbitrary continuous clock.
FEATURES
16-bit MPU bus compatible
Writing data via DMAC is possible
320-word (5,120-bit) static RAM
Data output rate of up to 10Mbps
Built-in function to add fixed data of a specified length at the be-
ginning of output data (Fixed data: Continuous High bit or Low bit
data)
The output format can be selected between FIFO or LIFO.
The output method can be selected from two:
(1)
Synchronized with an arbitrary continuous clock (
φ
IN) on the
system side; the frequency of clock output (CLK/
φ
OUT) can
be divided by 1, 2, 4, 8, or 16.
(2)
Synchronized with the data request clock (CLK IN) on the pe-
ripheral equipment side.
Up to two devices can be cascaded.
(1)
Toggle configuration
(2)
32-bit bus configuration
High fan-out outputs (CLK/
φ
OUT, DATA OUT).
Io=
±
24mA
(
±
4mA for INTR and DREQ
±
8mA for BUSY/ORDY)
PIN CONFIGURATION (TOP VIEW)
The clock input (CLK/
φ
IN) contains a Schmitt trigger.
The reset (RESET), Write (WR) and toggle input (TOG) contain
negative noise reduction circuits.
APPLICATION
Image-handling general OA equipment
Outline 32P4B
32P2W-A
BLOCK DIAGRAM
9
10
11
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
20
21
14
15
12
16
32
22
13
17
18
19
Write
control
circuit
D
Expansion
control
circuit
Clock
control
circuit
Reset
control
circuit
Command registers
Fixed data
length register
DREQ words register
Mode register
Frequency
divider
Clock signal
select circuit
Output
control
circuit
Write/send
address
control
circuit
320 word
CMOS
SRAM
P
Output
control
circuit
Output
control
circuit
Output
control
circuit
16
16
16
16
13
9
4
9
13
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
TOG
EXD
WR
CS
C/D
DACK
CLK/
φ
IN
CLKE
RESET
DREQ
INTR
BUSY/ORDY
DATA OUT
CLK/
φ
OUT
16
GND
V
CC