參數(shù)資料
型號(hào)： M66592FP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 0.50 MM PITCH, LQFP-64
文件頁數(shù)： 22/40頁
文件大?。?/td> 1583K
代理商： M66592FP
M66592F P/W G
Rev 1.00 2004.10.01 page 29 of 125
2.7 Interrupts enabled
Interrupts enabled register 0[INTENB0]
<Address: 30H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VBSE RSME SOFE
DVSE
CTRE BEMPE NRDYE BRDYE URST
SADR SCFG
SUSP WDST RDST
CMPL SERR
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15 VBSE
VBUS interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.8
2.7.1
2.7.4
14 RSME
Resume interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.9
2.7.1
2.7.4
13 SOFE
Frame number refresh interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.7
2.7.1
12 DVSE
Device state transition interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.5
2.7.1
2.7.2
11 CTRE
Control transfer stage transition interrupts
enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.6
2.7.1
2.7.3
10 BEMPE
Buffer Empty interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.4
2.7.1
9
NRDYE
Buffer Not Ready response interrupts
enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.3
2.7.1
8
BRDYE
Buffer Ready interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
3.2.2
2.7.1
7
URST
Default state transition notifications
enabled
0: DVST interrupt disabled at transition to
default state
1: DVST interrupt enabled at transition to default
state
R/W
R
3.2.5
2.7.2
6
SADR
Address state transition notifications
enabled
0: DVST interrupt disabled at transition to
address state
1: DVST interrupt enabled at transition to
address state
R/W
R
3.2.5
2.7.2
5
SCFG
Configuration state transition notifications
enabled
0: DVST interrupt disabled at transition to
configuration state
1: DVST interrupt enabled at transition to
configuration state
R/W
R
3.2.5
2.7.2
4
SUSP
Suspend state transition notifications
enabled
0: DVST interrupt disabled. at transition to
suspend state
1: DVST interrupt enabled at transition to
suspend state
R/W
R
3.2.5
2.7.2
3
WDST
Control write transfer status stage
transition notifications enabled
0: CTST interrupt disabled at transition to status
stage of control write transfer
1: CTST interrupt enabled at transition to status
stage of control write transfer
R/W
R
3.2.6
2.7.3
2
RDST
Control read transfer status stage
transition notifications enabled
0: CTST interrupt disabled at transition to status
stage of control read transfer
1: CTST interrupt enabled at transition to status
stage of control read transfer
R/W
R
3.2.6
2.7.3
1
CMPL
Control transfer end notifications enabled
0: CTST interrupt are disabled at end of control
transfer
1: CTST interrupt enabled at end of control
transfer
R/W
R
3.2.6
2.7.3
0
SERR
Control transfer sequence error
notifications enabled
0: CTST interrupt disabled at detection of
control transfer sequence error
1: CTST interrupt enabled at detection of control
transfer sequence error
R/W
R
3.2.6
2.7.3
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M66592FP#RB0Z 制造商:Renesas Electronics Corporation 功能描述:USB FS HOST-PERIPHERAL CONTROL 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:USB FS HOST-PERIPHERAL CONTROL
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M66592UG#RF0Z 制造商:Rochester Electronics LLC 功能描述: 制造商:RNS 功能描述:
M66592WG 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Peripheral Controller)
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