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參數(shù)資料
| 型號(hào)： | M66853J |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類(lèi)： | FIFO |
| 英文描述： | SRAM TYPE FIFO MEMORY |
| 中文描述： | FIFO存儲(chǔ)器SRAM的類(lèi)型 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大小： | 118K |
| 代理商： | M66853J |
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SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Enable to Output in High-Z
Reset to Flag and Output Valid time
t
REF
t
PAF
t
PAE
t
OE
t
OLZ
t
OHZ
t
RSF
Read Clock to Empty Flag
25
10
10
6
1
6
1
25
25
25
10
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
SKEW1
Clock Cycle Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS
(Ta=0 – 70C, Vcc=5V
±
10%, GND=0V)
Limits
Typ.
Min.
3
Max.
15
15
15
15
15
13
Symbol
Unit
Parameter
t
AC
t
WFF
Data Access Time
Write Clock to Full Flag
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CONDITIONS
(Ta=0 – 70C, Vcc=5V
±
10%, GND=0V)
Limits
Typ.
Min.
Max.
Symbol
Unit
Parameter
t
SKEW2
Skew time between Read Clock and Write Clock for Empty Flag and Full Flag
Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full
Flag
40
ns
3
13
25
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND – 3.0V
3ns
1.5V
1.5V
See Figure 4
D.U.T.
1.1k
30pF
680
5.0V
Figure 4. Output Load
Including Test board and scope capacitances.
5
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