MOTOROLA
M68060 USER’S MANUAL
xix
LIST OF ILLUSTRATIONS
1-1
1-2
2-1
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
6-3
MC68060 Block Diagram ...................................................................................1-6
Programming Model.........................................................................................1-12
Functional Signal Groups...................................................................................2-3
MC68060 Integer Unit Pipeline ..........................................................................3-1
Integer Unit User Programming Model...............................................................3-2
Integer Unit Supervisor Programming Model.....................................................3-3
Status Register...................................................................................................3-4
Processor Configuration Register ......................................................................3-5
Memory Management Unit.................................................................................4-2
Memory Management Programming Model.......................................................4-3
URP and SRP Register Formats........................................................................4-3
Translation Control Register Format ..................................................................4-4
Transparent Translation Register Format ..........................................................4-6
Translation Table Structure................................................................................4-8
Logical Address Format .....................................................................................4-8
Detailed Flowchart of Table Search Operation ................................................4-10
Detailed Flowchart of Descriptor Fetch Operation ...........................................4-11
Table Descriptor Formats.................................................................................4-12
Page Descriptor Formats .................................................................................4-12
Example Translation Table...............................................................................4-15
Translation Table Using Indirect Descriptors ...................................................4-16
Translation Table Using Shared Tables...........................................................4-18
Translation Table with Nonresident Tables......................................................4-19
Translation Table Structure for Two Tasks ......................................................4-21
Logical Address Map with Shared Supervisor and User Address Spaces.......4-22
Translation Table Using S-Bit and W-Bit To Set Protection.............................4-23
ATC Organization.............................................................................................4-24
ATC Entry and Tag Fields................................................................................4-25
Address Translation Flowchart.........................................................................4-29
MC68060 Instruction and Data Caches .............................................................5-2
Instruction Cache Line Format...........................................................................5-2
Data Cache Line Format....................................................................................5-2
Caching Operation .............................................................................................5-3
Cache Control Register......................................................................................5-5
Instruction Cache Line State Diagram..............................................................5-16
Data Cache Line State Diagrams.....................................................................5-18
Floating-Point Unit Block Diagram .....................................................................6-2
Floating-Point User Programming Model ...........................................................6-3
Floating-Point Control Register Format..............................................................6-4