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參數(shù)資料
| 型號： | M68AW031AM70NS6U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAC 6C 6#16S PIN PLUG |
| 中文描述： | 256千位（32K的× 8）3.0V異步SRAM |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 147K |
| 代理商： | M68AW031AM70NS6U |
M68AW031A
8/19
OPERATION
The M68AW031A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W and E as summarized in the Operat-
ing Modes table (see Table 6).
Table 6. Operating Modes
Note: X = V
IH
or V
IL
.
Read Mode
The M68AW031A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data of the 262,144 locations in
the static memory array, specified by the 15 ad-
dress inputs. Valid data will be available at the
eight output pins within t
AVQV
after the last stable
address, providing G is Low and E is Low. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limit-
ing parameter (t
ELQV
or t
GLQV
) rather than the ad-
dress. Data out may be indeterminate at t
ELQX
and
t
GLQX
but data lines will always be valid at t
AVQV
.
Figure 9. Address Controlled, Read Mode AC Waveforms
Note: E = Low, G = Low, W = High.
Operation
E
W
G
DQ0-DQ7
Power
Deselected
V
IH
X
X
Hi-Z
Standby (I
SB
)
Read
V
IL
V
IH
V
IL
Data Output
Active (I
CC
)
Write
V
IL
V
IL
X
Data Input
Active (I
CC
)
Output Disabled
V
IL
V
IH
V
IH
Hi-Z
Active (I
CC
)
AI05939
tAVAV
tAVQV
tAXQX
A0-A14
DQ0-DQ7
VALID
DATA VALID
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