參數(shù)資料
型號: M68AW127BL10N1T
廠商: 意法半導體
英文描述: 1Mbit 128K x8, 3.0V Asynchronous SRAM
中文描述: 1Mbit的128K的× 8,3.0V異步SRAM
文件頁數(shù): 3/20頁
文件大?。?/td> 327K
代理商: M68AW127BL10N1T
3/20
M68AW127B
SUMMARY DESCRIPTION
The M68AW127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
2.7 to 3.6V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AW127B is available in SO32, TSOP32
8x20mm and TSOP32 8x13.4mm packages.
Figure 2. Logic Diagram
Table 1. Signal Names
AI05972b
17
A0-A16
W
DQ0-DQ7
VCC
M68AW127B
G
VSS
8
E1
E2
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1
Chip Enable
E2
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
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