參數(shù)資料
型號(hào): M68AW127BN
廠商: 意法半導(dǎo)體
英文描述: 1Mbit 128K x8, 3.0V Asynchronous SRAM
中文描述: 1Mbit的128K的× 8,3.0V異步SRAM
文件頁數(shù): 10/20頁
文件大?。?/td> 327K
代理商: M68AW127BN
M68AW127B
10/20
Table 7. Read and Standby Mode AC Characteristics
Note: 1. Test conditions assume transition timing reference level = 0.3V
CC
or 0.7V
CC
.
2. At any given temperature and voltage condition, t
GHQZ
is less than t
GLQX
and t
EHQZ
is less than t
ELQX
for any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
Symbol
Parameter
M68AW127B
Unit
70
100
t
AVAV
Read Cycle Time
Min
70
100
ns
t
AVQV
Address Valid to Output Valid
Max
70
100
ns
t
AXQX (1)
Data hold from address change
Min
5
15
ns
t
EHQZ
(2,3)
Chip Enable High to Output Hi-Z
Max
25
30
ns
t
ELQV
Chip Enable Low to Output Valid
Max
70
100
ns
t
ELQX (1)
Chip Enable Low to Output Transition
Min
5
10
ns
t
GHQZ (2,3)
Output Enable High to Output Hi-Z
Max
25
30
ns
t
GLQV
Output Enable Low to Output Valid
Max
35
50
ns
t
GLQX (2)
Output Enable Low to Output Transition
Min
5
5
ns
t
PD (4)
Chip Enable or UB/LB High to Power Down
Max
0
0
ns
t
PU (4)
Chip Enable or UB/LB Low to Power Up
Min
70
100
ns
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