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參數(shù)資料
| 型號： | M68AW512DL70ZB6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 8 X 10 MM, 0.75 MM PITCH, ROHS COMPLIANT, TFBGA-48 |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 427K |
| 代理商： | M68AW512DL70ZB6F |
Obsolete
Product(s)
- Obsolete
Product(s)
M68AW512D
4/23
SUMMARY DESCRIPTION
The M68AW512D is an 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has a Chip
Select pin (E2) for easy memory expansion; when
it is active (E2 high) the device has an automatic
power-down feature, reducing the power con-
sumption by over 99%.
The M68AW512D is available in TFBGA48
(6x7mm, 0.75mm ball pitch) and TFBGA48
(8x10mm, 0.75mm ball pitch) packages.
In addition to the standard version, the packages
are also available in Lead-free version (standard
and Tape & Reel packing), in compliance with JE-
DEC Std J-STD-020B, and the RoHS (Restriction
of Hazardous Substances) directive. They are
also compliant with Lead-free soldering process-
es.
Figure 2. Logic Diagram
Table 1. Signal Names
AI04800b
19
A0-A18
W
DQ0-DQ15
VCC
M68AW512D
G
16
E1
UB
LB
VSS
E2
A0-A18
Address Inputs
DQ0-DQ15
Data Input/Output
E1
Chip Enable
E2
Chip Select
G
Output Enable
W
Write Enable
UB
Upper Byte Enable Input
LB
Lower Byte Enable Input
VCC
Supply Voltage
VSS
Ground
NC
Not Connected
DU
Don’t Use as Internally Connected
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| M68AW512DL70ZB6T | 制造商:STMicroelectronics 功能描述: |
| M68AW512DN55ZB1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
| M68AW512DN55ZB6 | 制造商:STMicroelectronics 功能描述: |
| M68AW512DN55ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
| M68AW512DN70ZB1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
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