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參數(shù)資料
| 型號(hào)： | M68AW512MN70ND1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit (512K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 8兆位（為512k × 16）3.0V異步SRAM |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 296K |
| 代理商： | M68AW512MN70ND1T |
M68AW512M
14/19
Table 8. Write Mode AC Characteristics
Note: 1. At any given temperature and voltage condition, t
WLQZ
is less than t
WHQX
for any given device.
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Symbol
Parameter
M68AW512M
Unit
55
70
t
AVAV
Write Cycle Time
Min
55
70
ns
t
AVBH
Address Valid to LB, UB High
Min
45
60
ns
t
AVBL
Address Valid to LB, UB Low
Min
0
0
ns
t
AVEH
Address Valid to Chip Enable High
Min
45
60
ns
t
AVEL
Address valid to Chip Enable Low
Min
0
0
ns
t
AVWH
Address Valid to Write Enable High
Min
45
60
ns
t
AVWL
Address Valid to Write Enable Low
Min
0
0
ns
t
BHAX
LB, UB High to Address Transition
Min
0
0
ns
t
BHDX
LB, UB High to Input Transition
Min
0
0
ns
t
BLBH
LB, UB Low to LB, UB High
Min
45
60
ns
t
BLEH
LB, UB Low to Chip Enable High
Min
45
60
ns
t
BLWH
LB, UB Low to Write Enable High
Min
45
60
ns
t
DVBH
Input Valid to LB, UB High
Min
25
30
ns
t
DVEH
Input Valid to Chip Enable High
Min
25
30
ns
t
DVWH
Input Valid to Write Enable High
Min
25
30
ns
t
EHAX
Chip Enable High to Address Transition
Min
0
0
ns
t
EHDX
Chip enable High to Input Transition
Min
0
0
ns
t
ELBH
Chip Enable Low to LB, UB High
Min
45
60
ns
t
ELEH
Chip Enable Low to Chip Enable High
Min
45
60
ns
t
ELWH
Chip Enable Low to Write Enable High
Min
45
60
ns
t
WHAX
Write Enable High to Address Transition
Min
0
0
ns
t
WHDX
Write Enable High to Input Transition
Min
0
0
ns
t
WHQX (1)
Write Enable High to Output Transition
Min
5
5
ns
t
WLBH
Write Enable Low to LB, UB High
Min
45
60
ns
t
WLEH
Write Enable Low to Chip Enable High
Min
45
60
ns
t
WLQZ (1,2)
Write Enable Low to Output Hi-Z
Max
20
20
ns
t
WLWH
Write Enable Low to Write Enable High
Min
45
60
ns
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