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參數(shù)資料
| 型號： | M68AW512MN70ND6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit (512K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 8兆位（為512k × 16）3.0V異步SRAM |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 296K |
| 代理商： | M68AW512MN70ND6T |
3/19
M68AW512M
SUMMARY DESCRIPTION
The M68AW512M is a 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW512M is available in TSOP44 Type II
packages.
Figure 2. Logic Diagram
Table 1. Signal Names
AI05835c
19
A0-A18
W
DQ0-DQ15
VCC
M68AW512M
G
16
E
UB
LB
VSS
A0-A16
Address Inputs
DQ0-DQ15
Data Input/Output
E
Chip Enable
G
Output Enable
W
Write Enable
UB
Upper Byte Enable Input
LB
Lower Byte Enable Input
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
DU
Don’t Use as Internally Connected
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