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參數(shù)資料
| 型號： | M68HC11K |
| 廠商： | Motorola, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 61/80頁 |
| 文件大?。?/td> | 420K |
| 代理商： | M68HC11K |
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M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
61
A multiplexer allows the single A/D converter to select one of 16 analog input signals.
The A/D converter control logic implements automatic conversion sequences on a selected channel
four times or on four channels once each. A write to the ADCTL register initiates conversions and, if
made while a conversion is in progress, a write to ADCTL also halts that conversion operation, sets
CCF, and proceeds to the next instruction.
When the SCAN bit is zero, four requested conversions are performed, once each, to fill the four result
registers. When SCAN is one, conversions continue in a round-robin fashion with the result registers
being updated as new data becomes available. When the MULT bit is zero, the A/D converter system
is configured to perform conversions on each channel in the group of four channels specified by the CD
and CC channel select bits.
Figure 15 Timing Diagram for a Sequence of Four A/D Conversions
Figure 16 Electrical Model of an Analog Input Pin (Sample Mode)
MSB
4
CYCLES
E CLOCK
WRITE
TO
ADCTL
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
END
12 E CYCLES
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
2
CYC
CONVERT FOURTH
CHANNEL
AND UPDATE ADDR4
CONVERT THIRD
CHANNEL
AND UPDATE ADDR3
CONVERT SECOND
CHANNEL
AND UPDATE ADDR2
CONVERT FIRST
CHANNEL
AND UPDATE ADDR1
SET
CCF
FLAG
REPEAT
SEQUENCE
IF
SCAN = 1
E
CYCLES
128
96
64
32
0
DAC
CAPACITANCE
VRL
ANALOG
INPUT
PIN
~
20 pF
+
~
20 V
–
~
0.7 V
< 2 pF
INPUT
PROTECTION
DEVICE
400 nA
JUNCTION
LEAKAGE
DIFFUSION AND
POLY COUPLER
≤
4 k
*
This analog switch is closed only during the 12-cycle sample time.
*
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