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參數(shù)資料
| 型號： | M68HC711D0CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, PLCC-44 |
| 文件頁數(shù)： | 67/124頁 |
| 文件大?。?/td> | 5398K |
| 代理商： | M68HC711D0CFN |
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RESETS AND INTERRUPTS
TECHNICAL DATA
5-3
Semiconductor wafer processing causes variations of the RC time-out values between
individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor
error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using
the clock monitor function when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock
monitor is enabled. Because the STOP function causes the clocks to be halted, the
clock monitor function generates a reset sequence if it is enabled at the time the STOP
mode was initiated. Before executing a STOP instruction, clear the CME bit in the OP-
TION register to zero to disable the clock monitor. After recovery from STOP, set the
CME bit to logic one to enable the clock monitor.
5.1.5 Option Register
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
Bits [7:6] and 2 — Not implemented
Always read zero
IRQE — Configure IRQ for Edge Sensitive Only Operation
This bit can be written only once during the first 64 E-clock cycles after reset in normal
modes.
0 = Low level recognition
1 = Falling edge recognition
DLY — Enable Oscillator Startup Delay
This bit is set during reset and can be written only once during the first 64 E-clock cy-
cles after reset in normal modes. If an external clock source rather than a crystal is
used, the stabilization delay can be inhibited because the clock source is assumed to
be stable.
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
CME — Clock Monitor Enable
This control bit can be read or written at any time and controls whether or not the in-
ternal clock monitor circuit triggers a reset sequence when the system clock is slow or
absent. When it is clear, the clock monitor circuit is disabled. When it is set, the clock
monitor circuit is enabled. Reset clears the CME bit.
CR[1:0] — COP Timer Rate Select
These control bits determine a scaling factor for the watchdog timer.
OPTION — System Configuration Options
$0039
Bit 7
654321
Bit 0
0
IRQE*
DLY*
CME
0
CR1*
CR0*
RESET:
00010000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| M68ICS05C | 功能描述:SIM PROGRAM FOR 68HC705C8A/C9A RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| M68ICS05JP | 功能描述:SIM PROGRAM FOR 68HC705JP7/JJ7 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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