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參數(shù)資料
| 型號： | M68LC302CPU20VCT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 0K |
| 描述： | IC MPU NETWORK 20MHZ 100-LQFP |
| 標準包裝： | 90 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 20MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
MC68LC302 PRODUCT INFORMATION
The SCP pins are now muxed with PA8, PA9, and PA10. The TXD3, RXD3, and RCLK3 functions asso-
ciated with SCC3 are eliminated.
The UDS, LDS, and R/W pins are not available except in slave mode, where they replace the IPL2-0 pins.
Instead, the new pins WEH, WEL, and OE have been defined for glueless interfacing to memory.
PA12 is now muxed with the MODCLK pin, which is associated with the 32 KHz or 4 MHz PLL. The MOD-
CLK pin is sampled after reset, and then becomes PA12.
New VCCSYN, GNDSYN, and XFC pins have been added in support of the on-chip PLL.
For purposes of emulation and development support only, a special 132 PGA version is supported. This
version adds back the FC2-0, IAC, FRZ, and AVEC pins. The FC2-0 pins allow bus cycles to be distin-
guished between program and data accesses, interrupt cycles, etc. The IAC, FRZ, and AVEC pins are
provided so that emulation vendors can quickly retrofit their existing MC68302 emulator designs to sup-
port the MC68LC302.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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