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參數(shù)資料
| 型號(hào)： | M6MGD13TW66CWG-P |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY & 67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM |
| 中文描述： | 134217728位（8388608字由16位）的CMOS閃存 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 131K |
| 代理商： | M6MGD13TW66CWG-P |
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
M6MGD13TW66CWG-P
Renesas LSIs
Rev.1.0.48a_bezb
1
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY &
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM
Stacked-CSP ( Chip Scale Package)
The M6MGD13TW66CWG-P is a Stacked Chip Scale
Package (S-CSP) that contents 128M-bit Flash memory and
64M-bit Mobile RAM in a 72-pin Stacked CSP with leaded
solder ball.
128M-bit Flash memory is a 8,388,608 words, single power
supply and high performance non-volatile memory fabricated
by CMOS technology for the peripheral circuit and DINOR IV
(Divided bit-line NOR IV) architecture for the memory cell. All
memory blocks are locked and can not be programmed or
erased, when F-WP# is Low. Using Software Lock Release
function, program or erase operation can be executed.
64M-bit Mobile RAM is a 4,194,304 words high density RAM
fabricated by CMOS technology for the peripheral circuit and
DRAM cell for the memory array. The interface is compatible to
an asynchronous SRAM.
The cells are automatically refreshed and the refresh control is
not required for system. The device also has the partial block
refresh scheme and the power down mode by writing the
command.
The M6MGD13TW66CWG-P is suitable for a high
performance cellular phone and a mobile PC that are
required to be small mounting area, weight and small power
dissipation.
Access Time Random Access/ Page Access
Flash
70ns /25ns (Max.)
Mobile RAM
85ns /25ns (Max.)
Supply Voltage
FM-VCC=2.7 ~ 3.0V
Ambient Temperature
Ta= -40 ~ 85 degree
Package
72pin S-CSP,
Ball pitch 0.80mm
Outer-ball:Sn-Pb
Application
Mobile communication products
A0-A21 : Common address for Flash/Mobile RAM
DQ0-DQ15 : Data I/O
F-CE1# : Flash chip enable 1
F-CE2# : Flash chip enable 2
F-OE# : Output enable for Flash Memory
F-WE# : Write enable for Flash Memory
M-CE# : Mobile RAM chip enable
M-OE# : Output enable for Mobile RAM
M-WE# : Write enable for Mobile RAM
M-LB# : Lower byte control for Mobile RAM
M-UB# : Upper byte control for Mobile RAM
NC : Non Connection
DU : Don’t Use
F-WP# : Write protect for Flash
F-RY/BY# : Flash Memory Ready /Busy
F-RP# : Reset power down for Flash
Description
Features
FM-VCC : VCC for Flash / Mobile RAM
GND
: GND for Flash / Mobile RAM
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
1
DQ15
RF-
GND
FM-
VCC
F-
OE#
GND
F-
CE1#
DQ1
DQ3
DQ5
DQ7
DQ14
DQ4
DQ2
DQ0
A1
A0
A2
A3
A6
DQ8
DQ9
DQ11
DQ10
DQ12
DQ6
DQ13
A9
A14
A13
A12
F-
A4
A7
A10
A15
A5
A8
A11
DU
DU
F-
WE#
GND
F-
WP#
M-
LB#
DU
DU
(Top View)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
8.5 mm
A18
A17
A16
A19
M-
UB#
A20
NC
F-
CE2#
NC
NC
NC
M-
OE#
DU
DU
DU
DU
NC
M-
WE#
DU
DU
M-
CE#
DU
DU
DU
A21
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