參數(shù)資料
型號(hào)： M72DW64000B90ZT
廠商： 意法半導(dǎo)體
英文描述： 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
中文描述： 64兆比特（x8 / x16插槽，多銀行，引導(dǎo)塊）和16Mbit的閃存?zhèn)戊o態(tài)存儲(chǔ)器，3V電源，多記憶體產(chǎn)品
文件頁(yè)數(shù)： 6/19頁(yè)
文件大?。?/td> 102K
代理商： M72DW64000B90ZT
M72DW64000B
6/19
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21).
Address lines A0-A19
are common inputs for the Flash Memory and
PSRAM components. Address line A20-A21 are
inputs for the Flash Memory component. The Ad-
dress Inputs select the cells in the memory array
to access during Bus Read operations. During Bus
Write operations they control the commands sent
to the Command Interface of the internal state ma-
chine. The Flash memory is accessed through the
Chip Enable (
E
F
) and Write Enable (W) signals,
while the PSRAM is accessed through two Chip
Enable signals (E1
S
and E2
S
) and the Write En-
able signal (W).
Data Inputs/Outputs (DQ0-DQ7).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
IH
. When BYTE is Low, V
IL
, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–
1).
When BYTE is High, V
IH
, this pin behaves as
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Flash-1 Chip Enable (E
F
).
The Chip Enable in-
put activates the memory to which it is attached,
allowing Bus Read and Bus Write operations to be
performed. When Chip Enable is High, V
IH
, all oth-
er pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the Flash Memory
and PSRAM components.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the Flash Memory and
PSRAM components.
V
PP/
Write Protect (V
PP
/WP).
The
Protect
pin provides two functions. The V
PP
func-
tion allows the Flash memory to use an external
high voltage power supply to reduce the time re-
V
PP
/Write
quired for Program operations. This is achieved
by bypassing the unlock cycles and/or using the
multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
When V
PP
/Write Protect is Low, V
IL
, the memory
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while V
PP
/Write Protect is Low, even when RP
F
is
at V
ID
.
When V
PP
/Write Protect
is High, V
IH
, the memory
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When V
PP
/Write Protect is raised to V
PP
the mem-
ory automatically enters the Unlock Bypass mode.
When V
PP
/Write Protect returns to V
IH
or V
IL
nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
PP
from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
IH
to V
PP
and from V
PP
to V
IH
must be slower
than t
VHVPP
. See the M29DW640D datasheet for
more details.
Never raise V
PP
/Write Protect to V
PP
from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The V
PP
/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1μF capacitor should be connected be-
tween the V
PP
/Write Protect pin and the V
SS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I
PP
.
Reset/Block Temporary Unprotect (RP
F
).
The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
PP
/WP is at V
IL
, then the two outer-
most boot blocks will remain protected even if RP
F
is at V
ID
.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
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