參數(shù)資料
型號: M74HC109
廠商: 意法半導體
英文描述: DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
中文描述: 雙JK觸發(fā)器亂竄預(yù)置和清除
文件頁數(shù): 5/11頁
文件大?。?/td> 249K
代理商: M74HC109
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
-40 to 85
o
C
74HC
Min.
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
Min.
Typ.
30
-55 to 125
o
C
54HC
Min.
Max.
75
15
13
150
30
26
150
30
26
Max.
95
19
16
190
38
32
190
38
32
Max.
110
22
19
225
45
38
225
45
38
t
TLH
t
THL
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
ns
8
7
t
PLH
t
PHL
Propagation
Delay Time
(CK-Q, Q)
50
16
13
50
16
13
17
59
67
15
6
6
15
6
6
17
5
4
ns
t
PLH
t
PHL
Propagation
Delay Time
(CLR, PR-Q, Q)
ns
f
MAX
Maximum Clock
Frequency
6.2
31
37
5
4.2
21
25
MHz
25
30
t
W(H)
t
W(L)
Minimum Pulse
Width (CLOCK)
75
15
13
75
15
13
75
15
13
0
0
0
50
10
9
10
95
19
16
95
19
16
95
19
16
0
0
0
65
13
11
10
110
22
19
110
22
19
110
22
19
0
0
0
75
15
13
10
ns
t
W(L)
Minimum Pulse
Width (CLR, PR)
ns
t
s
Minimum Set-up
Time
ns
t
h
Minimum Hold
Time
ns
t
REM
Minimum
Removal Time
(CLR, PR)
13
4
3
5
41
ns
C
IN
Input Capacitance
Power Dissipation
Capacitance
pF
C
PD
(*)
pF
(*) C
PD
isdefined asthe value ofthe IC’sinternal equivalent capactance which is calculated from the operating current consumption without load.
(Refer to Test Circuit).Average operting current can be obtained by thefollowingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/2(per Flip-flop)
M54/M74HC109
5/11
相關(guān)PDF資料
PDF描述
M74HC109C1R DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC109M1R DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC109B1R DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC10B1 TRIPLE 3-INPUT NAND GATE
M74HC10M1R TRIPLE 3-INPUT NAND GATE
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