參數(shù)資料
型號(hào): M74HC4017TTR
廠商: STMICROELECTRONICS
元件分類: 計(jì)數(shù)器
英文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16
封裝: TSSOP-16
文件頁數(shù): 1/12頁
文件大?。?/td> 377K
代理商: M74HC4017TTR
1/12
August 2001
s
HIGH SPEED :
tPD = 21 ns (TYP.) at VCC = 6V
s
LOW POWER DISSIPATION:
ICC =4A(MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4017
DESCRIPTION
The M74HC4017 is an high speed CMOS
DECADE COUNTER/DIVIDER fabricated with
silicon gate C2MOS technology.
The M74HC4017 is a 5-stage Johnson counter
with 10 decoded outputs. Each of the decoded
outputs is normally low and sequentially goes high
on the low to high transition of the clock input.
Each output stays high for one clock period of the
10 clock period cycle. The CARRY output goes
low to high after OUTPUT 10 goes low, and can
be used in conjunction with the CLOCK ENABLE
(CKEN)to cascade several stages.
The CLOCK ENABLE input disables counting
when in the high state. A CLEAR (CLR) input is
also provided which when taken high sets all the
decoded outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC4017
DECADE COUNTER/DIVIDER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC4017B1R
SOP
M74HC4017M1R
M74HC4017RM13TR
TSSOP
M74HC4017TTR
TSSOP
DIP
SOP
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