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參數(shù)資料
| 型號(hào)： | M74HC643RM13TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS INVERTING/NON INVERTING |
| 中文描述： | 八路總線收發(fā)器與三態(tài)輸出反向/非反相 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | M74HC643RM13TR |
M54/74HC245/640/643
M54/74HC245/640/643
October 1993
HC640 INVERTING, HC643 INVERTING/NON INVERTING
.
HIGH SPEED
t
PD
= 10 ns(TYP.) at V
CC
= 5V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) at T
A
= 25
o
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
INL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS245/640/643
OCTALBUS TRANSCEIVER (3-STATE):HC245 NONINVERTING
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTION
(top view)
DESCRIPTION
The M54/74HC245, HC640 and HC643 utilise
silicon gate C2MOStechnology to achive operating
speedsequivalent to LSTTL devices.
Alongwith the lowpower dissipation and high noise
immunity of standards C
2
MOS integrated circuit, it
possesses the capability to drive 15 LSTTL loads.
These IC’s are intended fortwo-way asynchronous
communication between data buses, and the
direction of data trasmission is determined by DIR
input. The enable input (G) can be used to disable
the device so thatthe busesare effectively isolated.
All input are equipped with protection circuits
against staticdischarge andtransientdischarge and
transient excess voltage.
IT IS PROHIBITED TO APPLY A SIGNAL TO A
BUS TERMINAL WHEN IT IS IN OUTPUT MODE
AND WHEN A BUS THERMINAL IS FLOATING
(HIGH IMPEDANCE STATE), IT IS REQUESTED
TO FIX THE INPUT LEVEL BY MEANS OF
EXTERNAL
PULL
DOWN
RESISTOR.
OR
PULL
UP
HC245
HC640
HC643
1/11
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