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參數(shù)資料
| 型號(hào)： | M74HC646 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Octal Bus Transceiver/Register(八總線收發(fā)器/寄存器(三態(tài))) |
| 中文描述： | 八路總線收發(fā)器/注冊(cè)（八總線收發(fā)器/寄存器（三態(tài)）） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 201K |
| 代理商： | M74HC646 |
M74HC646
M74HC648
October 1993
HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE,INV.)
.
HIGH SPEED
f
MAX
= 73 MHz (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS646/648
HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M74HCXXXB1R
M74HCXXXM1R
M1R
(Micro Package)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS
(top view)
GAB, GAB, CAB,
SAB,SBA, CBA
A, B
DESCRIPTION
The M74HC646/648 are highspeed CMOSOCTAL
BUS TRANSCEIVERS AND REGISTERS, (3-
STATE) fabricated in silicon gate C
2
MOS technol-
ogy. They have the same high speedperformance
of LSTTLcombined with trueCMOSlow powercon-
sumption.
These devices consist of bus transceiver circuits
with 3-state output, D-typeflip-flops,and control cir-
cuitry arranged for multiplexed transmission ofdata
directly from the input bus or from the internal reg-
isters.Dataonthe AorBbuswill be clocked intothe
registers on the low-to-high transition of theappro-
priate clockpin(ClockAB- orClockBA). Enable(G)
and direction (DIR) pins are provided to control the
transceiver functions. In thetransceiver mode, data
present at the high-impedance port may be stored
in either register or in both.
The select controls (Select AB select BA) can multi-
plex stored and real-time (transparent mode) data.
The direction control determines which bus will re-
ceivedata when enable G is active(low).
In theisolation mode (enable G high), ”A” data may
be stored in one register and/or ”B” data may be
storedinthe other register. When anoutput function
is disabled, the input function is still enabled and
may be used to store and transmit data. Only one
of the two buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
1/12
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