參數(shù)資料
型號: M74HC75
廠商: 意法半導體
英文描述: Low-Voltage Adjustable Precision Shunt Regulator 5-SOT-23 -40 to 125
中文描述: 4位D型鎖存
文件頁數(shù): 1/9頁
文件大?。?/td> 238K
代理商: M74HC75
M54HC75
M74HC75
December1992
4 BIT D TYPE LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HC75F1R
M74HC75B1R
M74HC75M1R
M74HC75C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
t
PD
= 10 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 2
μ
A (MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
= (OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS75
The M54/74HC75 is a high speed CMOS 4-BIT D-
TYPELATCHfabricated in silicongate C
2
MOStech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.Itcontains two groups of 2-bit latchescon-
trolled by anenable input (G1
2 orG3
4). These two
latch groups can be used in different circuits. Each
latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q).
Thedata appliedtothedata input istransfered tothe
QandQ outputs when theenable input is taken high
and the outputs willfollow the data input as long as
the enable input is kept high. When the enable input
is taken low, the information data applied to thedata
input is retained at the outputs. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
DESCRIPTION
1/9
相關(guān)PDF資料
PDF描述
M74HC75-1 Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 125
M74HC75B1R Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 125
M74HC75C1R Low-Voltage Adjustable Precision Shunt Regulator 6-SC70 -40 to 125
M74HC75M1R 4 BIT D TYPE LATCH
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