參數(shù)資料
型號(hào): M74HC76RM13TR
廠商: 意法半導(dǎo)體
英文描述: DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
中文描述: 雙JK觸發(fā)器亂竄預(yù)置和清除
文件頁(yè)數(shù): 1/11頁(yè)
文件大?。?/td> 508K
代理商: M74HC76RM13TR
1/11
August 2001
I
HIGH SPEED :
f
MAX
= 67MHz (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 76
I
I
I
I
I
I
DESCRIPTION
The M74HC76 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C
2
MOS technology.
Depending on with the logic level at J and K
inputs, this device changes state on the negative
going transition of clock pulse (CK). CLEAR (CLR)
and PRESET (PR) are independent of the clock
and are accomplished by a logic low on the
corresponding input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC76
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
TSSOP
M74HC76B1R
M74HC76M1R
M74HC76RM13TR
M74HC76TTR
TSSOP
DIP
SOP
相關(guān)PDF資料
PDF描述
M74HC76 Low-Voltage Adjustable Precision Shunt Regulator 3-TO-92 -40 to 125
M74HC76B1R DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC76C1R DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC76-1 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC77C1R 4-BIT D-TYPE LATCH
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