參數(shù)資料
型號: M74HC77M1R
廠商: 意法半導(dǎo)體
元件分類: 通用總線功能
英文描述: 4-BIT D-TYPE LATCH
中文描述: 4位D型鎖存
文件頁數(shù): 1/10頁
文件大小: 252K
代理商: M74HC77M1R
1/10
August 2001
I
HIGH SPEED :
t
PD
= 11 ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 77
I
I
I
I
I
I
DESCRIPTION
The M74HC77 is an high speed CMOS 4 BIT D
TYPE LATCH fabricated with silicon gate C
2
MOS
technology.
It contains two groups of 2 bit latches controlled by
an enable input (G1
2 or G3
4). These two latch
groups can be used in different circuits. The data
applied to the data inputs (1D, 2D, or 3D, 4D) are
transferred to the Q outputs (1Q, 2Q, or 3Q, 4Q)
respectively when the enable input (G1
2 or G3
4)
is taken high. The Q outputs will follow the data
inputs as long as the enable input is kept high.
When the enable input is taken low, the
information data applied to the data input is
retained at the Q outputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC77
4 BIT D TYPE LATCH
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
TSSOP
M74HC77B1R
M74HC77M1R
M74HC77RM13TR
M74HC77TTR
TSSOP
DIP
SOP
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