參數(shù)資料
型號(hào): M74HCT7259
廠商: 意法半導(dǎo)體
英文描述: 8 Bit Addressable Latch/Decoder/Relais Driver(8位可尋址鎖存器/譯碼器(開(kāi)漏極,反相輸出))
中文描述: 8位可尋址鎖存器/解碼器/信息Relais驅(qū)動(dòng)器(8位可尋址鎖存器/譯碼器(開(kāi)漏極,反相輸出))
文件頁(yè)數(shù): 1/11頁(yè)
文件大?。?/td> 218K
代理商: M74HCT7259
M74HCT7259
December1992
(OPEN DRAIN, INVERTING OUTPUT)
8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
90 LSTTL LOADS
.
HIGH CURRENT OPEN DRAIN OUTPUT UP
TO 80mA
B1R
(Plastic Package)
ORDER CODES :
M74HCT7259B1R
M74HCT7259M1R
M74HCT7259C1R
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
The
M74HCT7259
is ahigh speedCMOS8BITAD-
DRESSABLE LATCH/DECODER fabricated in sili-
con gate C2MOS technology. It has thesame high
speed performance of LSTTL combined with true
CMOS low powerconsumption.
The
M74HCT7259
has single data input (D) 8
LATCH inverted OUTPUTS (Q0-Q7), 3 address in-
puts (A, B and C), common enable input (ENABLE)
and a commonCLEAR input. To operate thisdevice
as anaddressable latch,data isheld onthe Dinput,
and the address of the latch into which the data is
to be entered is held on the A, B and C inputs.
When ENABLE is taken low the data flows through
totheaddress output. Thedataisstoredontheposi-
tive-going edge of the ENABLE pulse. All un-
adressed latches will remain unaffected. With
ENABLE in the high state the device is deselected
and all latches remain in theirprevious state, unaf-
fectedby changes onthedataoraddress inputs. To
eliminate the possibility of entering erroneous data
into the latches, the ENABLE should be held high
DESCRIPTION
INPUT AND OUTPUT EQUIVALENT CIRCUIT
1/11
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