參數(shù)資料
型號: M74HCT75RM13TR
廠商: 意法半導(dǎo)體
元件分類: 通用總線功能
英文描述: Dual N-Channel Logic Level UltraFET PowerMOSFET; Package: SO-8; No of Pins: 8; Container: Tape & Reel
中文描述: 4位D型鎖存
文件頁數(shù): 1/9頁
文件大?。?/td> 239K
代理商: M74HCT75RM13TR
M54HCT75
M74HCT75
January 1993
4 BIT D TYPE LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HCT75F1R
M74HCT75B1R
M74HCT75M1R
M74HCT75C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
t
PD
= 15 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 2
μ
A (MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2 V (MIN.) V
IL
= 0.8V (MAX.)
.
OUTPUTDRIVECAPABILITY 10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS75
TheM54/74HCT75isahighspeedCMOS4-BITD-TYPE
LATCH fabricated in silicon gate C2MOStechnology. It
has the same high speed performance of LSTTL com-
binedwithtrueCMOSlowpowerconsumption.Itcontains
twogroups of2-bit latchescontrolled by an enable input
(G1
2or G3
4).These two latchgroups can be used
indifferent circuits.EachlatchhasQand Qoutputs (1Q-
4Qand 1Q - 4Q). The data applied to the data input is
transfered totheQand Qoutputswhen theenable input
istaken high and the outputs will follow thedatainput as
long as the enable input is kept high. When the enable
inputistakenlow,theinformation dataapplied tothedata
inputisretained attheoutputs.Allinputsareequipped with
protection circuits against static discharge and transient
excessvoltage.Thisintegratedcircuithasinputandoutput
characteristicsthatarefullycompatible with54/74LSTTL
logic families. M54/74HCT devices are designed to di-
rectlyinterfaceHSC
2
MOSsystemswithTTLandNMOS
components. They are also plug in replacements for
LSTTLdevices givinga reductionofpowerconsumption.
DESCRIPTION
1/9
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