參數(shù)資料
型號(hào): M74VHC1GT32DTT1G
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/6頁(yè)
文件大?。?/td> 0K
描述: IC GATE OR SGL 2INP TTL 5TSOP
標(biāo)準(zhǔn)包裝: 1
系列: 74VHC
邏輯類型: 或門
電路數(shù): 1
輸入數(shù): 2
電源電壓: 3 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 8mA,8mA
邏輯電平 - 低: 0.53 V ~ 0.8 V
邏輯電平 - 高: 1.4 V ~ 2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 7.5ns @ 4.5V ~ 5.5V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 5-TSOP
封裝/外殼: 6-TSOP(0.059",1.50mm 寬)5 引線
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: M74VHC1GT32DTT1GOSDKR
Semiconductor Components Industries, LLC, 2013
July, 2013 Rev. 12
1
Publication Order Number:
MC74VHC1GT32/D
MC74VHC1GT32
2-Input OR Gate/CMOS
Logic Level Shifter
The MC74VHC1GT32 is an advanced high speed CMOS 2input
OR gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logiclevel translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the highvoltage power supply.
The MC74VHC1GT32 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT32 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 65; Equivalent Gates = 15
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
Figure 1. Pinout (Top View)
VCC
IN B
IN A
OUT Y
GND
IN A
IN B
OUT Y
≥ 1
Figure 2. Logic Symbol
1
2
3
4
5
http://onsemi.com
MARKING
DIAGRAMS
SC88A / SC705 / SOT353
DF SUFFIX
CASE 419A
TSOP5 / SOT235 / SC595
DT SUFFIX
CASE 483
1
5
PIN ASSIGNMENT
1
2
3
GND
IN B
IN A
4
5VCC
OUT Y
L
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
L
H
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
1
5
VN M G
G
VN
= Device Code
M
= Date Code*
G
= PbFree Package
1
5
VN M G
G
M
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)
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