參數(shù)資料
型號(hào)： M74VHC594TTR
廠商： 意法半導(dǎo)體
元件分類： 通用總線功能
英文描述： 8 BIT SHIFT REGISTER WITH OUTPUT REGISTER
中文描述： 8位元移位寄存器與輸出寄存器
文件頁數(shù)： 1/14頁
文件大?。?/td> 308K
代理商： M74VHC594TTR
1/14
November 2004
I
HIGH SPEED: t
PD
= 4.2ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 594
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (MAX.)
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74VHC594 is an high speed CMOS 8-BIT
SHIFT REGISTERS fabricated with sub-micron
silicon gate C
2
MOS technology.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding
clear (SCLR, RCLR) are provided for both the shift
register and the storage register.
A serial (QH’) output is provided for cascading
purposes.
Both the shift register and storage
register use positive-edge triggered clocks. If the
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74VHC594
8 BIT SHIFT REGISTER
WITH OUTPUT REGISTER
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
M74VHC594RMTR
M74VHC594TTR
TSSOP
SOP
Rev. 5
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