- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180240 > M7A3P400-FG144 FPGA, 400000 GATES, 350 MHz, PBGA144 PDF資料下載
參數(shù)資料
| 型號： | M7A3P400-FG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| 封裝： | 1 MM PITCH, FBGA-144 |
| 文件頁數(shù)： | 191/246頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | M7A3P400-FG144 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁當(dāng)前第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁
ProASIC3/E Flash Family FPGAs
v2.1
2-37
For boards and cards with three levels of staging, card
power supplies must have time to reach their final value
before the I/Os are connected. Pay attention to the sizing
of power supply decoupling capacitors on the card to
ensure that the power supplies are not overloaded with
capacitance.
Cards with three levels of staging should have the
following sequence:
Grounds
Powers
I/Os and other pins
For Level 3 and Level 4 compliance with the A3P030
device, cards with two levels of staging should have the
following sequence:
Grounds
Powers, I/Os, and other pins
Cold-Sparing Support
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
The A3P030 device fully supports cold-sparing, since the I/O
clamp diode is always off (see Table 2-13 on page 2-31).
For other ProASIC3 devices, since the I/O clamp diode is
always active, cold-sparing can be accomplished either by
employing a bus switch to isolate the device I/Os from the
rest of the system or by driving each ProASIC3 I/O pin to
0V.
If the A3P030 is used in applications requiring cold-
sparing, a discharge path from the power supply to
ground should be provided. This can be done with a
discharge resistor or a switched resistor. This is necessary
because the A3P030 does not have built-in I/O clamp
diodes.
If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitor is
in parallel with the resistor). The RC time constant should
ensure full discharge of supplies before cold-sparing
functionality is required. The resistor is necessary to
ensure that the power pins are discharged to ground
every time there is an interruption of power to the
device.
Electrostatic Discharge (ESD) Protection
ProASIC3 devices are tested per JEDEC Standard
JESD22-A114-B.
ProASIC3 devices contain clamp diodes at every I/O,
global, and power pad. Clamp diodes protect all device
pads against damage from ESD as well as from excessive
voltage transients.
ProASIC3 devices are tested to the following models: the
Human Body Model (HBM) with a tolerance of 2,000 V,
the Machine Model (MM) with a tolerance of 250 V, and
the Charged Device Model (CDM) with a tolerance of
200 V.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND and its N side connected to the
pad. During operation, these diodes are normally
biased in the off state, except when transient voltage is
significantly above VCCI or below GND levels.
In A3P030, the first diode is always off. On other
ProASIC3 devices, the clamp diode is always on and
cannot be switched off.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-17 on page 2-38 for
more information about the I/O standards and the clamp
diode.
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3P400-FG256I | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| M7A3P400-FG256 | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| M7A3P400-FG484I | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| M7A3P400-FG484 | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| M7A3P400-FGG144I | FPGA, 400000 GATES, 350 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。