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參數(shù)資料
| 型號： | M87C257-70XC1TR |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM |
| 中文描述： | 地址鎖存256K 32K的× 8紫外線EPROM和檢察官辦公室存儲器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 143K |
| 代理商： | M87C257-70XC1TR |
Mode
E
G
A9
ASV
PP
Q0 - Q7
Read (Latched Address)
V
IL
V
IL
X
V
IL
Data Out
Read (Applied Address)
V
IL
V
IL
X
V
IH
Data Out
Output Disable
V
IL
V
IH
X
X
Hi-Z
Program
V
IL
Pulse
V
IH
X
V
PP
Data In
Verify
V
IH
V
IL
X
V
PP
Data Out
Program Inhibit
V
IH
V
IH
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Electronic Signature
V
IL
V
IL
V
ID
V
IL
Codes
Note
: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V
Table 3. Operating Modes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
1
0
0
0
0
0
0
0
80h
Table 4. Electronic Signature
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable (AS = V
IH
) or latched (AS =
V
IL
), the address access time (t
AVQV
) is equal to the
delay from E to output (t
ELQV
). Data is available at
the output after delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The proc-
essor multiplexed bus (AD0-AD7) may be tied to
the M87C257’s address and data pins. No sepa-
rate address latch is needed because the
M87C257 latches all address inputs when AS is
low.
Standby Mode
The M87C257 has a standby mode which reduces
the active current from 30mA to 100
μ
A (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the G
input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
3/13
M87C257
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相關代理商/技術參數(shù) |
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|---|---|
| M87C257-70XC1X | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM |
| M87C257-70XC3TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM |
| M87C257-70XC3X | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM |
| M87C257-70XC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM |
| M87C257-70XC6X | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM |
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