M902-01 Datasheet Rev 2.1
4
of 8
Revised 24Jun2004
Integrated Circuit Systems, Inc.
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Integrated
Circuit
Systems, Inc.
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
A
PPLICATION
I
NFORMATION
This section includes information on the optional
external crystal and on the external loop filter.
The subsections on the loop filter provide example
component values and also briefly describe the SAW
PLL simulator tool and additional application
information available at www.icst.com.
External Crystal Specifications
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should have the following general specifications:
Crystal Specifications
Parameter
Crystal Type
Mode of Oscillation
f
0
Nominal Frequency Range
f/f
0
f/f
C
/ T
A
Frequency Stability
-40
to +
85
o
C
1
The external crystal will be applied to the
XTAL_1 / REF_IN
and
XTAL_2
input pins. External crystal load capacitors
are also required.
Recommended External Crystal Configuration
M902-01
Figure 4: Recommended External Crystal Configuration
XTAL= 25 or 30 MHz, Load Capacitance Specification = 18 pF
C1
= 27 pF
C2
= 33 pF
External load capacitors C1 and C2 present a load of 15 pf
to the crystal (they are seen in series by the crystal through
the common ground connection). With the additional of PCB
trace capacitance and M902-01 input capacitance, the total
load to the crystal is about 18 pf.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M902-01 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 5).
R
LOOP
C
LOOP
Figure 5: External Loop Filter
The loop filter is implemented as a differential circuit
to minimize system noise interference. Due to the
differential signal path design, the implementation
requires two identical complementary RC filters as
shown here. See Table 4, External Loop Filter
Component Values, below.
Refer to the M902-01 product web page at
www.icst.com/products/summary/m902-01.htm for
additional product information.
Min Typ Max
AT-cut quartz
Fundamental
16
Unit
40
MHz
ppm
Frequency Tolerance @
+
25
o
C
1
Note 1: These frequency tolerance specifications are suitable for
a
±
100 ppm clock output frequency requirement.
±
15
±
50
ppm
f/f
0
/ y Aging, per year (first) @
+
25
o
C
1
ESR
Equivalent Series Resistance
C
S
Shunt Capacitance
Spurious Response (non-harmonic)
±
5
ppm
pF
50
7
-
40
dBc
C
L
Load Capacitance,
parallel load resonant
Drive Level
16
32
pF
P
0
0.1
1.0
mW
Table 3: External Loop Filter Component Values
XTAL_2
XTAL
XTAL OSC
XTAL_1 / REF_IN
C1
C2
External Loop Filter Component Values
PLL Bandwidth
(
kHz
)
Factor
Damping
R loop
(
k
)
C loop
(
μ
F
)
R post
(
k
)
C post
(
pF
)
0.5
1.5
1
2.1
2
6.4
10.6
3
3.0
3.3
1.1
4.5
4.2
1.5
4.7
4.7
20.0
33.0
4.70
1.00
0.10
0.10
0.03
20
10
10
20
20
150
150
150
270
120
Note 1: Optimum loop bandwidth when using an external reference
crystal. Will help to attenuate interference on the crystal’s
sinusoidal clock waveform and therefore will minimize
device output clock jitter.
Note 2: Alternative loop filter setting when using an external refer-
ence crystal. Smaller C loop lowers loop damping factor with
negligible increase in output jitter.
Note 3: Optimum loop bandwidth when using an external reference
crystal oscillator. The square wave clock reference does not
require as much jitter attenuation, which allows for a wider
loop bandwidth and improved system noise tolerance.
Table 4: External Loop Filter Component Values
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
C
LOOP
OP_IN
nOP_IN
6
7
5
4
9
8