參數(shù)資料
型號(hào): M93C46DW
廠商: 意法半導(dǎo)體
英文描述: 16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit 8-bit or 16-bit wide
中文描述: 16Kbit,8Kbit,4Kbit,2Kbit,1Kbit和256 8位或16位全
文件頁(yè)數(shù): 19/31頁(yè)
文件大?。?/td> 611K
代理商: M93C46DW
19/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6)
Note: 1. t
CHCL
+ t
CLCH
1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W or G or S.
Test conditions specified in
Table 13.
and
Table 10.
Symbol
Alt.
Parameter
Min.
3
Max.
3
Min.
4
Max.
4
Unit
f
C
f
SK
Clock Frequency
D.C.
1
D.C.
2
MHz
t
SLCH
Chip Select Low to Clock High
250
50
ns
t
SHCH
t
CSS
Chip Select Set-up Time
100
50
ns
t
SLSH2
t
CS
Chip Select Low to Chip Select High
1000
200
ns
t
CHCL1
t
SKH
Clock High Time
350
200
ns
t
CLCH1
t
SKL
Clock Low Time
250
200
ns
t
DVCH
t
DIS
Data In Set-up Time
100
50
ns
t
CHDX
t
DIH
Data In Hold Time
100
50
ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S)
100
50
ns
t
CLSL
t
CSH
Chip Select Hold Time
0
0
ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status
400
200
ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z
200
100
ns
t
CHQL
t
PD0
Delay to Output Low
400
200
ns
t
CHQV
t
PD1
Delay to Output Valid
400
200
ns
t
W
t
WP
Erase/Write Cycle time
10
5
ms
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