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INSTRUCTIONS
The M93C86/C76/C66/C56/C46/C06have seven
instructions,as shown in Table7. Eachinstruction
isprecededby therising edge of thesignalapplied
on the S input (assuming that the clock C is low).
Afterthe deviceis selected,the internallogicwaits
for the start bit, which definesthe beginningof the
instructionbitstream.Thestartbitisthefirst’1’read
on the D input during the rising edge of the clock
C. Following the start bit, the op-codes of the
instructions are made up of the 2 following bits.
Notethat someinstructionsuseonlythesefirsttwo
bits,othersuse alsothefirsttwobitsof theaddress
todefinetheop-code.Theop-codeis thenfollowed
by the address of the byte/word to be accessed.
FortheM93C06andM93C46,theaddressis made
up of 6 bitsfor thex16 organizationor 7bits forthe
x8 organization (see Table 7A). For the M93C56
and M93C66, the addressis made up of 8 bits for
thex16organizationor9bitsforthex8organization
(seeTable7B).For the M93C76 and M93C86,the
addressis madeup of 10bitsfor thex16organiza-
tion or 11 bits for the x8 organization (see Table
7C).
TheM93Cx6isfabricatedinCMOStechnologyand
is therefore able to run from 0Hz (static input sig-
nals)up tothe maximumratings(specifiedin Table
6).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READinstruction
is received, the instruction and address are de-
codedand thedatafromthememoryis transferred
intoan outputshiftregister.Adummy’0’bitisoutput
firstfollowedby the8bitbyteor the16bitwordwith
the MSB first. Output data changes are triggered
by the Low to Hightransition of the Clock (C). The
M93Cx6 will automatically increment the address
andwillclockout thenextbyte/wordas longas the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOToutput between bytes/words
and a continuousstreamof datacan be read.
Erase/WriteEnableand Disable
The Erase/Write Enable instruction (EWEN)
authorizesthefollowingErase/Writeinstructionsto
be executed. The Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions and the internal program-
mingcyclecannotrun. Whenpower isfirstapplied,
theM93Cx6is in Erase/WriteDisablemodeand all
Erase/Write instructions are inhibited. When the
EWENinstructionis executed,Erase/Writeinstruc-
tions remain enabled until an Erase/Write Disable
instruction(EWDS) is executedor V
CC
falls below
the power-on reset Threshold voltage. To protect
thememory contentsfrom accidentalcorruption,it
is advisable to issue the EWDS instruction after
every write cycle. The READ instruction is not
affectedby the EWEN or EWDS instructions.
Erase
The Erase instruction (ERASE) programs the ad-
dressedmemory byte or word bits to ’1’. Once the
addressiscorrectlydecoded,thefallingedgeof the
ChipSelectinput(S)startsaself-timederasecycle.
If the M93Cx6 is still performing the erase cycle,
theBusysignal(Q= 0)willbereturnedif Sis driven
high after the t
SLSH
delay, and the M93Cx6 will
ignoreany dataon the bus. When the erase cycle
iscompleted,the Readysignal (Q= 1) will indicate
(if S is driven high) that the M93Cx6 is ready to
receivea new instruction.
Write
The Write instruction (WRITE) is composedof the
Op-Code followed by the address and the 8 or 16
databits tobe written.Datainputis sampledon the
Low to High transition of the clock. After the last
data bit has been sampled, Chip Select (S) must
be brought Low before the next rising edge of the
clock (C) in order to start the self-timed program-
mingcycle Thisis important as,if Sis broughtlow
before or after this specific frame window, the
addressedlocation will not be programmed.
IftheM93Cx6is stillperformingthewrite cycle,the
Busy signal (Q = 0) will be returned if S is driven
high after the t
SLSH
delay, and the M93Cx6 will
ignore any data on the bus. When the write cycle
iscompleted,the Readysignal (Q= 1) will indicate
(if S is driven high) that the M93Cx6 is ready to
receive a new instruction. Programming is inter-
nallyself-timed(theexternalclocksignalon Cinput
may be disconnectedor leftrunning after the start
of a Writecycle). The Writeinstructionincludesan
automaticErase cycle beforewriting the data, it is
thereforeunnecessaryto executean Eraseinstruc-
tion beforea Write instruction execution.
EraseAll
The Erase All instruction(ERAL) erasesthe whole
memory (all memory bits are set to ’1’). A dummy
addressis inputduring the instructiontransferand
the erase is made in the sameway as the ERASE
instruction above. If the M93Cx6is stillperforming
the erase cycle, the Busy signal (Q = 0) will be
returnedif Sisdriven highafterthet
SLSH
delay,and
theM93Cx6 will ignore anydata onthe bus.When
the erase cycle is completed, the Ready signal (Q
= 1) will indicate (if S is driven high) that the
M93Cx6 is ready to receivea new instruction.
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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06