參數(shù)資料
型號: M93S56-DS6TP
廠商: 意法半導(dǎo)體
英文描述: Quadruple 2-Input Positive-NAND Gates 14-SO -40 to 85
中文描述: 4Kbit,2Kbit和1Kbit 16位寬MICROWIRE串行EEPROM的訪問與街區(qū)保護(hù)
文件頁數(shù): 27/34頁
文件大小: 525K
代理商: M93S56-DS6TP
27/34
M93S66, M93S56, M93S46
Figure 12. Synchronous Timing (Read or Write)
PRE
W
C
S
D
Hi-Z
tW
tDVCH
AI02027
Q
tCLPRX
tSLWX
tCLSL
tCHDX
tSLSH
tSLQZ
BUSY
tSHQV
READY
WRITE CYCLE
ADDRESS/DATA INPUT
An
A0/D0
tSLCH
相關(guān)PDF資料
PDF描述
M93S56-DS6TG Quadruple 2-Input Positive-NAND Gates 14-SO -40 to 85
M93S56-DS6T Quadruple 2-Input Positive-NAND Gates 14-SO -40 to 85
M93S56-DS6P Quadruple 2-Input Positive-NAND Gates 14-PDIP -40 to 85
M93S56-DS6G Quadruple 2-Input Positive-NAND Gates 14-PDIP -40 to 85
M93S56-WMN3G 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection
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