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參數(shù)資料
| 型號： | M95020-BN6P |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 4Kbit，2Kbit和1Kbit SPI總線串行EEPROM的高速時鐘 |
| 文件頁數(shù)： | 17/37頁 |
| 文件大?。?/td> | 586K |
| 代理商： | M95020-BN6P |
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M95040, M95020, M95010
Write to Memory Array (WRITE)
As shown in
Figure 13.
, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High after the rising edge of Serial Clock
(C) that latches the last data bit, and before the
next rising edge of Serial Clock (C) occurs any-
where on the bus. In the case of
Figure 13.
, this
occurs after the eighth bit of the data byte has
been latched in, indicating that the instruction is
being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t
WC
(as specified in
Table 18.
to
Table 22.
), at the end
of which the Write in Progress (WIP) bit is reset to
0.
If, though, Chip Select (S) continues to be driven
Low, as shown in
Figure 14.
, the next byte of input
data is shifted in. In this way, all the bytes from the
given address to the end of the same page can be
programmed in a single instruction.
If Chip Select (S) still continues to be driven Low,
the next byte of input data is shifted in, and is used
to overwrite the byte at the start of the current
page.
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
if a Write cycle is already in progress
–
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the rising edge of Serial Clock
(C) that latches the last data bit, and before
the next rising edge of Serial Clock (C) occurs
anywhere on the bus)
–
if Write Protect (W) is Low or if the addressed
page is in the region protected by the Block
Protect (BP1 and BP0) bits.
Figure 13. Byte Write (WRITE) Sequence
Note: Depending on the memory size, as shown in
Table 6.
, the most significant address bits are Don’t Care.
AI01442D
C
D
S
Q
A7
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
A6 A5 A4 A3 A2 A1 A0
A8
20 21 22 23
High Impedance
Instruction
Byte Address
0
7
6
5
4
3
2
0
1
Data Byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M95020-BN6G | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020BN | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-WBN6TG | 10-Bit Buffers/Drivers With 3-State Outputs 24-PDIP -40 to 85 |
| M95020-WBN6T | 10-Bit Buffers/Drivers With 3-State Outputs 24-SO -40 to 85 |
| M95020-WBN6P | 10-Bit Buffers/Drivers With 3-State Outputs 24-SO -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95020-BN6P/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-BN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-BN6T/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-BN6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-BN6TG/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
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