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參數資料
| 型號： | M95020-RBN6G |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-LQFP 0 to 70 |
| 中文描述： | 4Kbit，2Kbit和1Kbit SPI總線串行EEPROM的高速時鐘 |
| 文件頁數： | 14/37頁 |
| 文件大?。?/td> | 586K |
| 代理商： | M95020-RBN6G |
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M95040, M95020, M95010
14/37
Read Status Register (RDSR)
One of the major uses of this instruction is to allow
the MCU to poll the state of the Write In Progress
(WIP) bit. This is needed because the device will
not accept further WRITE or WRSR instructions
when the previous Write cycle is not yet finished.
As shown in
Figure 10.
, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte are then shifted in, on
Serial Data Input (D). The current state of the bits
in the Status Register is shifted out, on Serial Data
Out (Q). The Read Cycle is terminated by driving
Chip Select (S) High.
The Status Register may be read at any time, even
during a Write cycle (whether it be to the memory
area or to the Status Register). All bits of the Sta-
tus Register remain valid, and can be read using
the RDSR instruction. However, during the current
Write cycle, the values of the non-volatile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes avail-
able when a new RDSR instruction is executed, af-
ter completion of the Write cycle. On the other
hand, the two read-only bits (Write Enable Latch
(WEL), Write In Progress (WIP)) are dynamically
updated during the on-going Write cycle.
The status and control bits of the Status Register
are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit.
The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits.
The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in
Table 4.
) be-
comes
protected
against
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
Write
(WRITE)
Figure 10. Read Status Register (RDSR) Sequence
C
D
S
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
0
AI01444D
Q
7
6
5
4
3
2
1
0
Status Register Out
High Impedance
MSB
7
6
5
4
3
2
1
0
Status Register Out
MSB
7
相關PDF資料 |
PDF描述 |
|---|---|
| M95020-RBN6 | Octal Registered Transceivers With 3-State Outputs 24-SSOP -40 to 85 |
| M95020-RBN3TP | Octal Registered Transceivers With 3-State Outputs 24-SSOP -40 to 85 |
| M95020-RBN3TG | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN3T | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN3P | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M95020-RBN6G/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN6P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN6P/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN6T/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
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