- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359116 > M95020-RDW3TG (意法半導(dǎo)體) 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock PDF資料下載
參數(shù)資料
| 型號： | M95020-RDW3TG |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 4Kbit，2Kbit和1Kbit SPI總線串行EEPROM的高速時(shí)鐘 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 586K |
| 代理商： | M95020-RDW3TG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
13/37
M95040, M95020, M95010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in
Figure 8.
, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
Figure 8. Write Enable (WREN) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in
Figure 9.
, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
–
Power-up
–
WRDI instruction execution
–
WRSR instruction completion
–
WRITE instruction completion
–
Write Protect (W) line being held Low.
Figure 9. Write Disable (WRDI) Sequence
C
D
AI01441D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
C
D
AI03790D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M95020-RDW3T | 512 x 18 x 2 Clocked Bidirectional First-In, First-Out Memory 80-LQFP 0 to 70 |
| M95020-RDW3P | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RDW3G | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RBN6TP | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-LQFP 0 to 70 |
| M95020-RBN6TG | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-LQFP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95020-RDW3TG/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RDW3TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RDW3TP/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RDW6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-RDW6/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。