參數(shù)資料
型號(hào): M95020-RMN6G
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 4Kbit,2Kbit和1Kbit SPI總線串行EEPROM的高速時(shí)鐘
文件頁(yè)數(shù): 28/37頁(yè)
文件大小: 586K
代理商: M95020-RMN6G
M95040, M95020, M95010
28/37
Table 21. AC Characteristics (M950x0-W, Device Grade 3)
Note: 1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Previous product: identified by Process Identification letter K.
4. Present product: identified by Process Identification letter W or G.
Test conditions specified in
Table 11.
and
Table 9.
Symbol
Alt.
Parameter
Min.
3
Max.
3
Min.
4
Max.
4
Unit
f
C
f
SCK
Clock Frequency
D.C.
2
D.C.
5
MHz
t
SLCH
t
CSS1
S Active Setup Time
200
90
ns
t
SHCH
t
CSS2
S Not Active Setup Time
200
90
ns
t
SHSL
t
CS
S Deselect Time
200
100
ns
t
CHSH
t
CSH
S Active Hold Time
200
90
ns
t
CHSL
S Not Active Hold Time
200
90
ns
t
CH 1
t
CLH
Clock High Time
200
90
ns
t
CL 1
t
CLL
Clock Low Time
200
90
ns
t
CLCH 2
t
RC
Clock Rise Time
1
1
μs
t
CHCL 2
t
FC
Clock Fall Time
1
1
μs
t
DVCH
t
DSU
Data In Setup Time
40
20
ns
t
CHDX
t
DH
Data In Hold Time
50
30
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
t
HLCH
Clock Low Hold Time after HOLD Active
90
40
ns
t
CHHL
Clock High Set-up Time before HOLD Active
t
CH
60
ns
t
CHHH
Clock High Set-up Time before HOLD not
Active
t
CH
60
ns
t
SHQZ 2
t
DIS
Output Disable Time
250
100
ns
t
CLQV
t
V
Clock Low to Output Valid
150
60
ns
t
CLQX
t
HO
Output Hold Time
0
0
ns
t
QLQH 2
t
RO
Output Rise Time
100
50
ns
t
QHQL 2
t
FO
Output Fall Time
100
50
ns
t
HHQV
t
LZ
HOLD High to Output Valid
100
50
ns
t
HLQZ 2
t
HZ
HOLD Low to Output High-Z
250
100
ns
t
W
t
WC
Write Time
10
5
ms
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