參數(shù)資料
型號: M95020-SBN3T
廠商: 意法半導體
元件分類: DRAM
英文描述: 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 4Kbit,2Kbit和1Kbit SPI總線串行EEPROM的高速時鐘
文件頁數(shù): 5/37頁
文件大小: 586K
代理商: M95020-SBN3T
5/37
M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically eras-
able programmable memory (EEPROM), access-
ed by a high speed SPI-compatible bus. The other
members of the family (M95020 and M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Each device is accessed by a simple serial inter-
face that is SPI-compatible. The bus signals are C,
D and Q, as shown in
Table 2.
and
Figure 2.
.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instruc-
tions are disabled by Write Protect (W).
Figure 2. Logic Diagram
Figure 3. DIP, SO and TSSOP Connections
Note: See
PACKAGE MECHANICAL
section for package dimen-
sions, and how to identify pin-1.
Table 2. Signal Names
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
HOLD
Hold
V
CC
Supply Voltage
V
SS
Ground
D
VSS
C
HOLD
Q
W
S
VCC
AI01790D
M95xxx
1
2
3
4
8
7
6
5
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