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參數(shù)資料
| 型號： | M95020-WDW6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 4Kbit，2Kbit和1Kbit SPI總線串行EEPROM的高速時鐘 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大小： | 586K |
| 代理商： | M95020-WDW6T |
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M95040, M95020, M95010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in
Figure 8.
, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
Figure 8. Write Enable (WREN) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in
Figure 9.
, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
–
Power-up
–
WRDI instruction execution
–
WRSR instruction completion
–
WRITE instruction completion
–
Write Protect (W) line being held Low.
Figure 9. Write Disable (WRDI) Sequence
C
D
AI01441D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
C
D
AI03790D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M95020-WDW6TG | 8-Bit to 9-Bit Parity Bus Transceivers 24-PDIP -40 to 85 |
| M95020-WDW6TP | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-WMN3TG | 10-Bit Bus-Interface D-Type Latches With 3-State Outputs 24-SOIC -40 to 85 |
| M95020-WMN3TP | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-WMN5T | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95020-WDW6T/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-WDW6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-WDW6TG/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95020-WDW6TP | 功能描述:電可擦除可編程只讀存儲器 2.5 V to 5.5V 2K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M95020-WDW6TP/S | 制造商:STMicroelectronics 功能描述:EEPROM SERL-SPI 2KBIT 256X8 3.3V/5V 8TSSOP - Tape and Reel |
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