參數(shù)資料
型號(hào): M95020MN
廠商: 意法半導(dǎo)體
英文描述: 9-Bit Bus-Interface D-Type Latches With 3-State Outputs 24-SSOP -40 to 85
中文描述: 4Kbit,2Kbit和1Kbit SPI總線串行EEPROM的高速時(shí)鐘
文件頁(yè)數(shù): 8/37頁(yè)
文件大小: 586K
代理商: M95020MN
M95040, M95020, M95010
8/37
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in
Figure 5.
, is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI Modes Supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
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