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參數(shù)資料
| 型號： | M95080-DL1T |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 64/32/16/8千位串行SPI總線的EEPROM高速時鐘 |
| 文件頁數(shù)： | 9/39頁 |
| 文件大?。?/td> | 590K |
| 代理商： | M95080-DL1T |
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9/39
M95640, M95320
OPERATING FEATURES
Power-up
When the power supply is turned on, V
CC
rises
from V
SS
to V
CC
.
During this time, the Chip Select (S) must be al-
lowed to follow the V
CC
voltage. It must not be al-
lowed to float, but should be connected to V
CC
via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all oper-
ations are disabled and the device will not respond
to any command.
A stable and valid V
CC
must be applied before ap-
plying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V
CC
.
Active Power and Stand-by Power Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode. The device
consumes I
CC
, as specified in Tables 13 to 17.
When Chip Select (S) is High, the device is dis-
abled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Stand-by
Power mode, and the device consumption drops
to I
CC1
.
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
7).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 7 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) being Low.
Figure 7. Hold Condition Activation
AI02029D
HOLD
C
Hold
Condition
Hold
Condition
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