參數(shù)資料
型號(hào): M95080-MN5T
廠商: 意法半導(dǎo)體
元件分類: FIFO
英文描述: 64 x 36 x 2 bidirectional synchronous FIFO memory 132-BQFP 0 to 70
中文描述: 64/32/16/8千位串行SPI總線的EEPROM高速時(shí)鐘
文件頁數(shù): 20/39頁
文件大?。?/td> 590K
代理商: M95080-MN5T
M95640, M95320
20/39
POWER-UP AND DELIVERY STATE
Power-up State
After Power-up, the device is in the following state:
– Stand-by mode
– deselected (after Power-up, a falling edge is re-
quired on Chip Select (S) before any instruc-
tions can be started).
– not in the Hold Condition
– the Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
the SRWD, BP1 and BP0 bits of the Status Regis-
ter are unchanged from the previous power-down
(they are non-volatile bits).
INITIAL DELIVERY STATE
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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